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2.5 V to 5.5 V, 400 A, Quad Voltage Output 8-/10-/12-Bit DACs in 16-Lead TSSOP AD5307/AD5317/AD5327*
FEATURES AD5307: 4 Buffered 8-Bit DACs in 16-Lead TSSOP A Version: 1 LSB INL, B Version: 0.625 LSB INL AD5317: 4 Buffered 10-Bit DACs in 16-Lead TSSOP A Version: 4 LSB INL, B Version: 2.5 LSB INL AD5327: 4 Buffered 12-Bit DACs in 16-Lead TSSOP A Version: 16 LSB INL, B Version: 10 LSB INL Low Power Operation: 400 A @ 3 V, 500 A @ 5 V 2.5 V to 5.5 V Power Supply Guaranteed Monotonic by Design over All Codes Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin) Double-Buffered Input Logic Buffered/Unbuffered Reference Input Options Output Range: 0 V to VREF or 0 V to 2 VREF Power-On Reset to 0 V Simultaneous Update of Outputs (LDAC Pin) Asynchronous Clear Facility (CLR Pin) Low Power, SPI(R), QSPITM, MICROWIRETM, and DSP Compatible 3-Wire Serial Interface SDO Daisy-Chaining Option On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range -40 C to +105 C APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control GENERAL DESCRIPTION
The AD5307/AD5317/AD5327 are quad 8-, 10-, and 12-bit buffered voltage-output DACs in a 16-lead TSSOP package that operate from a single 2.5 V to 5.5 V supply, consuming 400 mA at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/ms. The AD5307/ AD5317/AD5327 utilize a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards. The references for the four DACs are derived from two reference pins (one per DAC pair). These reference inputs can be configured as buffered or unbuffered inputs. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. There is also an asynchronous active low CLR pin that clears all DACs to 0 V. The outputs of all DACs may be updated simultaneously using the asynchronous LDAC input. The parts contain a power-down feature that reduces the current consumption of the devices to 300 nA @ 5 V (90 nA @ 3 V). The parts may also be used in daisy-chaining applications using the SDO pin. All three parts are offered in the same pinout, which allows users to select the amount of resolution appropriate for their application without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
VDD VREFAB GAIN-SELECT LOGIC DAC REGISTER STRING DAC A
AD5307/AD5317/AD5327
LDAC INPUT REGISTER
BUFFER
VOUTA
SCLK INTERFACE LOGIC
INPUT REGISTER
DAC REGISTER
STRING DAC B
BUFFER
VOUTB
SYNC
DIN
INPUT REGISTER
DAC REGISTER
STRING DAC C
BUFFER
VOUTC
INPUT REGISTER SDO
DAC REGISTER
STRING DAC D
BUFFER POWER-DOWN LOGIC
VOUTD
POWER-ON RESET DCEN LDAC CLR VREFCD
PD
GND
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.
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AD5307/AD5317/AD5327-SPECIFICATIONS GND; C = 200 pF to GND; all specifications T to T , unless otherwise noted.)
L MIN MAX
(VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k
to
Parameter
1 3, 4
A Version2 Min Typ Max
B Version2 Min Typ Max
Unit
Conditions/Comments
DC PERFORMANCE AD5307 Resolution Relative Accuracy Differential Nonlinearity AD5317 Resolution Relative Accuracy Differential Nonlinearity AD5327 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Lower Deadband5 Upper Deadband5 Offset Error Drift6 Gain Error Drift6 DC Power Supply Rejection Ratio6 DC Crosstalk6 DAC REFERENCE INPUTS6 VREF Input Range VREF Input Impedance (RDAC) 74 37 Reference Feedthrough Channel-to-Channel Isolation OUTPUT CHARACTERISTICS6 Minimum Output Voltage7 Maximum Output Voltage7 DC Output Impedance Short Circuit Current Power-Up Time 1 0.25
8 0.15 0.02 10 0.5 0.05 12 2 0.2 5 0.3 10 10
1 0.25
8 0.15 0.02 10 0.5 0.05 12 2 0.2 5 0.3 10 10
Bits 0.625 LSB 0.25 LSB Bits LSB LSB
Guaranteed Monotonic by Design over All Codes
4 0.5
2.5 0.5
Guaranteed Monotonic by Design over All Codes
16 1 60 1.25 60 60
10 1 60 1.25 60 60
-12 -5
-12 -5
Guaranteed Monotonic by Design over All Codes mV VDD = 4.5 V, Gain = 2; See Figures 4 and 5 % of FSR VDD = 4.5 V, Gain = 2; See Figures 4 and 5. mV See Figure 4. Lower deadband exists only if offset error is negative. mV See Figure 5. Upper deadband exists only if VREF = VDD and offset plus gain error is positive. ppm of FSR/C ppm of FSR/C dB mV VDD = 10% RL = 2 kW to GND or VDD Buffered Reference Mode Unbuffered Reference Mode Buffered Reference Mode and Power-Down Mode Unbuffered Reference Mode. 0 V to VREF Output Range Unbuffered Reference Mode. 0 V to 2 VREF Output Range Frequency = 10 kHz Frequency = 10 kHz This is a measure of the minimum and maximum drive capability of the output amplifier. VDD = 5 V VDD = 3 V Coming out of Power-Down Mode. VDD = 5 V Coming out of Power-Down Mode. VDD = 3 V
Bits LSB LSB
-60 200 VDD VDD >10 90 45 -90 -75 0.001 VDD - 0.001 0.5 25 16 2.5 5 74 37 1 0.25
-60 200 VDD VDD >10 90 45 -90 -75 0.001 VDD - 0.001 0.5 25 16 2.5 5
V V MW kW kW dB dB V V W mA mA ms ms
-2-
REV. A
AD5307/AD5317/AD5327
Parameter
1 6
A Version2 Min Typ Max 1 0.8 0.6 0.5 1.7
B Version2 Min Typ Max 1 0.8 0.6 0.5 1.7
Unit mA V V V V
Conditions/Comments
LOGIC INPUTS Input Current VIL, Input Low Voltage VIH, Input High Voltage (Excluding DCEN) VIH, Input High Voltage (DCEN)
VDD = 5 V 10% VDD = 3 V 10% VDD = 2.5 V VDD = 2.5 V to 5.5 V; TTL and 1.8 V CMOS Compatible VDD = 5 V 10% VDD = 3 V 10% VDD = 2.5 V
2.4 2.1 2.0 3
6
2.4 2.1 2.0 3
Pin Capacitance LOGIC OUTPUT (SDO) VDD = 4.5 V to 5.5 V Output Low Voltage, VOL Output High Voltage, VOH VDD = 2.5 V to 3.6 V Output Low Voltage, VOL Output High Voltage, VOH Floating State Leakage Current Floating State Output Capacitance POWER REQUIREMENTS VDD IDD (Normal Mode)8 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V
V V V pF
0.4 VDD - 1 0.4 VDD - 0.5 3 2.5 500 5.5 900 2.5 500 1 VDD - 0.5 3 VDD - 1
0.4
V V V V mA pF
ISINK = 2 mA ISOURCE = 2 mA ISINK = 2 mA ISOURCE = 2 mA DCEN = GND DCEN = GND
0.4 1
5.5 900
V mA mA mA mA VIH = VDD and VIL = GND All DACs in Unbuffered Mode. In Buffered Mode, extra current is typically x mA per DAC where x = 5 mA + VREF/RDAC. VIH = VDD and VIL = GND
400 0.3 0.09
750 1 1
400 0.3 0.09
750 1 1
NOTES 1 See the Terminology section. 2 Temperature range (A, B Versions): -40C to +105C; typical at +25C. 3 DC specifications tested with the outputs unloaded, unless stated otherwise. 4 Linearity is tested using a reduced code range: AD5307 (Code 8 to 255); AD5317 (Code 28 to 1023); AD5327 (Code 115 to 4095). 5 This corresponds to x codes. x = Deadband Voltage/LSB size. 6 Guaranteed by design and characterization; not production tested. 7 For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V REF = VDD and offset plus gain error must be positive. 8 Interface inactive. All DACs active. DAC outputs unloa-ded. Specifications subject to change without notice.
REV. A
-3-
AD5307/AD5317/AD5327 AC CHARACTERISTICS1
Parameter2 Output Voltage Settling Time AD5307 AD5317 AD5327 Slew Rate Major-Code Change Glitch Energy Digital Feedthrough SDO Feedthrough Digital Crosstalk Analog Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion
(VDD = 2.5 V to 5.5 V; RL = 2 k otherwise noted.)
Min A, B Versions3 Typ Max 6 7 8 0.7 12 0.5 4 0.5 1 3 200 -70 8 9 10
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
Unit ms ms ms V/ms nV-s nV-s nV-s nV-s nV-s nV-s kHz dB
Conditions/Comments VREF = VDD = 5 V 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0) 1/4 Scale to 3/4 Scale Change (0x100 to 0x300) 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00) 1 LSB Change around Major Carry Daisy-Chain Mode; SDO Load is 10 pF
VREF = 2 V 0.1 V p-p. Unbuffered Mode VREF = 2.5 V 0.1 V p-p. Frequency = 10 kHz
NOTES 1 Guaranteed by design and characterization; not production tested. 2 See the Terminology section. 3 Temperature range (A, B Versions): -40C to +105C; typical at +25C. Specifications subject to change without notice.
TIMING CHARACTERISTICS1, 2, 3 (V
Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t134, 5 t145 t155 t165 A, B Versions Limit at TMIN, TMAX 33 13 13 13 5 4.5 0 50 20 20 20 0 20 25 5 8 0
DD
= 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.)
Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns max ns min ns min ns min Conditions/Comments SCLK Cycle Time SCLK High Time SCLK Low Time SYNC to SCLK Falling Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC High Time LDAC Pulsewidth SCLK Falling Edge to LDAC Rising Edge CLR Pulsewidth SCLK Falling Edge to LDAC Falling Edge SCLK Rising Edge to SDO Valid (VDD = 3.6 V to 5.5 V) SCLK Rising Edge to SDO Valid (VDD = 2.5 V to 3.5 V) SCLK Falling Edge to SYNC Rising Edge SYNC Rising Edge to SCLK Rising Edge SYNC Rising Edge to LDAC Falling Edge
NOTES 1 Guaranteed by design and characterization; not production tested. 2 All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 See Figures 2 and 3. 4 This is measured with the load circuit of Figure 1. t 13 determines maximum SCLK frequency in Daisy-Chain mode. 5 Daisy-chain mode only. Specifications subject to change without notice.
-4-
REV. A
AD5307/AD5317/AD5327
2mA IOL
TO OUTPUT PIN
CL 50pF 2mA IOH
VOH (MIN)
Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications
t1
SCLK
t8
SYNC
t4
t3
t2
t7
t5
DIN DB15
t6
DB0
t9 t12
LDAC1
t10
LDAC2
t11
CLR NOTES 1ASYNCHRONOUS LDAC UPDATE MODE. 2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Interface Timing Diagram
t1
SCLK
t8
SYNC
t4
t3
t2
t14
t15 t16
LDAC
t9
t5
DIN DB15
t6
DB0 DB15' INPUT WORD FOR DAC (N+1) DB15 UNDEFINED INPUT WORD FOR DAC N DB0 DB0'
INPUT WORD FOR DAC N SDO
t13
Figure 3. Daisy-Chaining Timing Diagram
REV. A
-5-
AD5307/AD5317/AD5327
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Digital Input Voltage to GND . . . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to GND . . . . . -0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . -0.3 V to VDD + 0.3 V VOUTA-VOUTD to GND . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Versions) . . . . . . . . . . . . -40C to +105C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150C
16-Lead TSSOP Power Dissipation . . . . . . . . . . . . . . . . . . (TJ max - TA)/ JA JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model AD5307ARU AD5307ARU-REEL 7 AD5307BRU AD5307BRU-REEL AD5307BRU-REEL7 AD5317ARU AD5317ARU-REEL7 AD5317BRU AD5317BRU-REEL AD5317BRU-REEL7 AD5327ARU AD5327ARU-REEL7 AD5327BRU AD5327BRU-REEL AD5327BRU-REEL7
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5307/AD5317/AD5327 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
-6-
REV. A
AD5307/AD5317/AD5327
PIN CONFIGURATION
CLR 1 LDAC 2 VDD 3 VOUTA 4
16
SDO SYNC SCLK
DIN TOP VIEW VOUTB 5 (Not to Scale) 12 GND
13
AD5307/ AD5317/ AD5327
15 14
VOUTC 6 VREFAB 7 VREFCD 8
11 10 9
VOUTD PD DCEN
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2
Mnemonic CLR LDAC
Function Active Low Control Input that Loads All Zeros to All Input and DAC Registers. Therefore, the outputs also go to 0 V. Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC Registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently low. Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 mF capacitor in parallel with a 0.1 mF capacitor to GND. Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Reference Input Pin for DACs A and B. It may be configured as a buffered or an unbuffered input to each or both of the DACs, depending on the state of the BUF bits in the serial input words to DACs A and B. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. Reference Input Pin for DACs C and D. It may be configured as a buffered or an unbuffered input to each or both of the DACs, depending on the state of the BUF bits in the serial input words to DACs C and D. It has an input range from 0.25 V to VDD in unbuffered mode and from 1 V to VDD in buffered mode. This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a daisy chain. The pin should be tied low if it is being used in standalone mode. Active low control input that acts as a hardware power-down option. All DACs go into power-down mode when this pin is tied low. The DAC outputs go into a high impedance state and the current consumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V). Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. Ground Reference Point for All Circuitry on the Part. Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The DIN input buffer is powered down after each write cycle. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle. Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock.
3 4 5 6 7
VDD VOUTA VOUTB VOUTC VREFAB
8
VREFCD
9 10
DCEN PD
11 12 13 14
VOUTD GND DIN SCLK
15
SYNC
16
SDO
REV. A
-7-
AD5307/AD5317/AD5327
TERMINOLOGY Relative Accuracy Major-Code Transition Glitch Energy
For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in TPCs 1, 2, and 3.
Differential Nonlinearity
Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11).
Digital Feedthrough
Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in TPCs 4, 5, and 6.
Offset Error
Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to the (SYNC held high). It is specified in nV-s and is measured with a fullscale change on the digital input pins, i.e., from all 0s to all 1s or vice versa.
Digital Crosstalk
This is a measure of the offset error of the DAC and the output amplifier. (See Figures 4 and 5.) It can be negative or positive. It is expressed in mV.
Gain Error
This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.
Offset Error Drift
This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-s.
Analog Crosstalk
This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
Gain Error Drift
This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/C.
DC Power Supply Rejection Ratio (PSRR)
This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping LDAC high. Then pulse LDAC low and monitor the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied 10%.
DC Crosstalk
This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in mV.
Reference Feedthrough
This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with LDAC low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion
This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in dB.
This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC, and the THD is a measure of the harmonics present on the DAC output. It is measured in dB.
-8-
REV. A
AD5307/AD5317/AD5327
GAIN ERROR + OFFSET ERROR
OUTPUT VOLTAGE GAIN ERROR + OFFSET ERROR UPPER DEADBAND CODES
OUTPUT VOLTAGE
ACTUAL IDEAL POSITIVE OFFSET ERROR DAC CODE
NEGATIVE OFFSET ERROR
DAC CODE ACTUAL IDEAL
FULL SCALE
Figure 5. Transfer Function with Positive Offset (VREF = VDD)
LOWER DEADBAND CODES AMPLIFIER FOOTROOM
NEGATIVE OFFSET ERROR
Figure 4. Transfer Function with Negative Offset
REV. A
-9-
AD5307/AD5317/AD5327-Typical Performance Characteristics
1.0 TA = 25 C VDD = 5V 0.5
INL ERROR (LSB)
INL ERROR (LSB)
3 TA = 25 C VDD = 5V 2
12 TA = 25 C VDD = 5V
8 INL ERROR (LSB)
1
4 0
0
0 -1
-4
-0.5
-2
-8 -12
-1.0
0
50
100
150 CODE
200
250
-3
0
200
400 600 CODE
800
1000
0
1000
2000 CODE
3000
4000
TPC 1. AD5307 Typical INL Plot
TPC 2. AD5317 Typical INL Plot
TPC 3. AD5327 Typical INL Plot
0.3
TA = 25 C VDD = 5V
0.6
TA = 25 C VDD = 5V
1.0
0.2
DNL ERROR (LSB) DNL ERROR (LSB)
0.4
0.5 DNL ERROR (LSB)
TA = 25 C VDD = 5V
0.1
0.2
0
0
0
-0.1
-0.2 -0.4 -0.6 0
-0.5
-0.2
-0.3
0
50
100 150 CODE
200
250
200
400 600 CODE
800
1000
-1.0 0
1000
2000 CODE
3000
4000
TPC 4. AD5307 Typical DNL Plot
TPC 5. AD5317 Typical DNL Plot
TPC 6. AD5327 Typical DNL Plot
0.50
VDD = 5V TA = 25 C
0.5 0.4
MAX INL
VDD = 5V VREF = 3V
1.0
VDD = 5V VREF = 2V
MAX INL
0.3 0.2
ERROR (LSB)
MAX DNL
0.25
0.1 0 -0.1
MIN DNL MAX DNL
0.5
ERROR (% FSR)
ERROR (LSB)
GAIN ERROR
0
MIN DNL
0
OFFSET ERROR
-0.2
-0.25
MIN INL
-0.5
MIN INL
-0.3 -0.4
-0.50
0
1
2 3 VREF (V)
4
5
-0.5
-1.0
40 0 40 80 120 TEMPERATURE ( C)
40
0
40
80
120
TEMPERATURE ( C)
TPC 7. AD5307 INL and DNL Error vs. VREF
TPC 8. AD5307 INL Error and DNL Error vs. Temperature
TPC 9. AD5307 Offset Error and Gain Error vs. Temperature
-10-
REV. A
AD5307/AD5317/AD5327
0.2 0.1 0 TA = 25 C VREF = 2V
5 5V SOURCE 3V SOURCE
VOUT (V)
600 500 TA = 25 C VDD = 5V VREF = 2V
4
GAIN ERROR
ERROR (% FSR)
400
IDD ( A)
5V SINK 3V SINK
-0.1 -0.2 -0.3 -0.4 -0.5 -0.6 OFFSET ERROR
3
300
2
200
1
100 0
0
1
2
3 VDD (V)
4
5
6
0
0
1 3 4 2 5 SINK/SOURCE CURRENT (mA)
6
ZERO SCALE CODE
FULL SCALE
TPC 10. Offset Error and Gain Error vs. VDD
TPC 11. VOUT Source and Sink Current Capability
TPC 12. Supply Current vs. DAC Code
600 -40 C +25 C 500
0.5
800
DECREASING
TA = 25 C
0.4
700 INCREASING
400
IDD ( A)
IDD ( A)
+105 C 300
IDD ( A)
0.3 -40 C 0.2 +25 C 0.1 +105 C
600 VDD = 5V 500
200
100 0 2.5
400
INCREASING DECREASING VDD = 3V 4 5
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
0 2.5
3.0
3.5
4.0 VDD (V)
4.5
5.0
5.5
300
0
1
2 3 VLOGIC (V)
TPC 13. Supply Current vs. Supply Voltage
TPC 14. Power-Down Current vs. Supply Voltage
TPC 15. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing and Decreasing
CH1
TA = 25 C 5s VDD = 5V VREF = 5V
CH1
VOUTA
TA = 25 C VDD = 5V VREF = 2V
CH1
TA = 25 C VDD = 5V VREF = 2V VOUTA
VDD
SCLK
CH2
CH2
VOUTA
CH2
PD
CH1 1V, CH2 5V, TIME BASE= 1 s/DIV
CH1 2.00V, CH2 200mV, TIME BASE = 200 s/DIV
CH1 500mV, CH2 5.00V, TIME BASE = 1 s/DIV
TPC 16. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
TPC 17. Power-On Reset to 0 V
TPC 18. Exiting Power-Down to Midscale
REV. A
-11-
AD5307/AD5317/AD5327
2.50
10 0 -10
VDD = 3V
FREQUENCY
VDD = 5V
VOUT (V)
2.49
-20
dB
-30
2.48
-40 -50
2.47
350
400
450 500 IDD ( A)
550
600
1 s/DIV
-60 10
100
1k 10k 100k FREQUENCY (Hz)
1M
10M
TPC 19. IDD Histogram with VDD = 3 V and VDD = 5 V
TPC 20. AD5327 Major-Code Transition Glitch Energy
TPC 21. Multiplying Bandwidth (Small-Signal Frequency Response)
0.02 VDD = 5V TA = 25 C
FULL-SCALE ERROR (V)
0.01
0
-0.01
-0.02
0
1
2
3 VREF (V)
4
5
6
1mV/DIV
150ns/DIV
TPC 22. Full-Scale Error vs. VREF
TPC 23. DAC-to-DAC Crosstalk
-12-
REV. A
AD5307/AD5317/AD5327
FUNCTIONAL DESCRIPTION
The AD5307/AD5317/AD5327 are quad resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits respectively. Each contains four output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/ms. DACs A and B share a common reference input, VREFAB. DACs C and D share a common reference input, VREFCD. Each reference input may be buffered to draw virtually no current from the reference source, or unbuffered to give a reference input range from 0.25 V to VDD. The devices have a power-down mode in which all DACs may be turned off completely with a high impedance output.
Digital-to-Analog Section
impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to headroom and footroom of the reference amplifier.
R R R TO OUTPUT AMPLIFIER
R R
The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the VREF pin provides the reference voltage for the corresponding DAC. Figure 6 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by
Figure 7. Resistor String
VOUT =
where:
VREF D 2N
If there is a buffered reference in the circuit (e.g., REF192), there is no need to use the on-chip buffers of the AD5307/AD5317/ AD5327. In unbuffered mode, the input impedance is still large at typically 90 kW per reference input for 0 V to VREF mode and 45 kW for 0 V to 2 VREF mode. The buffered/unbuffered option is controlled by the BUF bit in the data-word. The BUF bit setting applies to whichever DAC is selected.
Output Amplifier
D = decimal equivalent of the binary code that is loaded to the DAC register: 0-255 for AD5307 (8 bits) 0-1023 for AD5317 (10 bits) 0-4095 for AD5327 (12 bits) N = DAC resolution
VREF AB
The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of VREF, GAIN, offset error, and gain error. If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to VREF. If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 VREF. Because of clamping, however, the maximum output is limited to VDD - 0.001 V. The output amplifier is capable of driving a load of 2 kW to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11.
BUF
REFERENCE BUFFER GAIN MODE (GAIN = 1 OR 2)
INPUT REGISTER
DAC REGISTER
RESISTOR STRING OUTPUT BUFFER AMPLIFIER
VOUTA
The slew rate is 0.7 V/ms with a half-scale settling time to 0.5 LSB (at eight bits) of 6 ms.
POWER-ON RESET
Figure 6. Single DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 7. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.
DAC Reference Inputs
The AD5307/AD5317/AD5327 are provided with a power-on reset function so that they power up in a defined state. The power-on state is Normal operation Reference inputs unbuffered 0 V to VREF output range Output voltage set to 0 V
There is a reference pin for each pair of DACs. The reference inputs are buffered but can also be individually configured as unbuffered. The advantage with the buffered input is the high
Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.
REV. A
-13-
AD5307/AD5317/AD5327
SERIAL INTERFACE
The AD5307/AD5317/AD5327 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
BUF Controls whether reference of the addressed DAC is buffered or unbuffered. 0: Unbuffered reference. 1: Buffered reference. The AD5327 uses all 12 bits of DAC data; the AD5317 uses 10 bits and ignores the 2 LSB. The AD5307 uses eight bits and ignores the last four bits. The data format is straight binary, with all 0s corresponding to 0 V output and all 1s corresponding to full-scale output (VREF - 1 LSB). The SYNC input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while SYNC is low. To start the serial data transfer, SYNC should be taken low, observing the minimum SYNC to SCLK falling edge setup time, t4. After SYNC goes low, serial data will be shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. In standalone mode (DCEN = 0), any data and clock pulses after the 16th falling edge of SCLK will be ignored and no further serial data transfer will occur until SYNC is taken high and low again. SYNC may be taken high after the falling edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to SYNC rising edge time, t7. After the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected DAC. If SYNC is taken high before the 16th falling edge of SCLK, the data transfer will be aborted and the DAC input registers will not be updated.
The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2. The 16-bit word consists of four control bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. Data is loaded MSB first (Bit 15), and the first two bits determine whether the data is for DAC A, DAC B, DAC C, or DAC D. Bits 13 and 12 control the operating mode of the DAC. Bit 13 is GAIN, which determines the output range of the part. Bit 12 is BUF, which controls whether the reference inputs are buffered or unbuffered.
Table I. Address Bits for the AD53x7
A1 (Bit 15) 0 0 1 1
Control Bits
A0 (Bit 14) 0 1 0 1
DAC Addressed DAC A DAC B DAC C DAC D
GAIN Controls the output range of the addressed DAC. 0: Output range of 0 V to VREF. 1: Output range of 0 V to 2 VREF.
BIT 15 (MSB) A1 A0 GAIN BUF D7 D6 D5 D4
BIT 0 (LSB) D3 D2 D1 D0 X X X X
DATA BITS
Figure 8. AD5307 Input Shift Register Contents
BIT 15 (MSB) A1 A0 GAIN BUF D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X BIT 0 (LSB) X
DATA BITS
Figure 9. AD5317 Input Shift Register Contents
BIT 15 (MSB) A1 A0 GAIN BUF D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 BIT 0 (LSB) D0
DATA BITS
Figure 10. AD5327 Input Shift Register Contents
-14-
REV. A
AD5307/AD5317/AD5327
When data has been transferred into the input register of a DAC, the corresponding DAC register and DAC output can be updated by taking LDAC low. CLR is an active low, asynchronous clear that clears the input registers and DAC registers to all 0s.
Low Power Serial Interface
To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, i.e., on the falling edge of SYNC. The SCLK and DIN input buffers are powered down on the rising edge of SYNC.
Daisy-Chaining
These parts contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5307/AD5317/AD5327, the part will update the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk.
Load DAC Input (LDAC)
For systems that contain several DACs, or where the user wishes to read back the DAC contents for diagnostic purposes, the SDO pin may be used to daisy-chain several devices together and provide serial readback. By connecting the DCEN (daisy-chain enable) pin high, the daisy-chain mode is enabled. It is tied low in the case of standalone mode. In daisy-chain mode, the internal gating on SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC is low. If more than 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting this line to the DIN input on the next DAC in the chain, a multi-DAC interface is constructed. Sixteen clock pulses are required for each DAC in the system. Therefore, the total number of clock cycles must equal 16N, where N is the total number of devices in the chain. When the serial transfer to all devices is complete, SYNC should be taken high. This prevents any further data from being clocked into the input shift register. A continuous SCLK source may be used if it can be arranged that SYNC is held low for the correct number of clock cycles. Alternatively, a burst clock containing the exact number of clock cycles may be used and SYNC may be taken high some time later. When the transfer to all input registers is complete, a common LDAC signal updates all DAC registers and all analog outputs are updated simultaneously.
Double-Buffered Interface
LDAC transfers data from the input registers to the DAC registers (and, therefore, updates the outputs). Use of the LDAC function enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes: Synchronous Mode: In this mode, the DAC registers are updated after new data is read in on the falling edge of the 16th SCLK pulse. LDAC can be tied permanently low or pulsed as in Figure 2. Asynchronous Mode: In this mode, the outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the DAC registers are updated with the contents of the input register.
POWER-DOWN MODE
The AD5307/AD5317/AD5327 have low power consumption, typically dissipating 1.2 mW with a 3 V supply and 2.5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into powerdown mode, which is selected by taking the PD pin low. When the PD pin is high, all DACs work normally with a typical power consumption of 500 mA at 5 V (400 mA at 3 V). However, in power-down mode, the supply current falls to 300 nA at 5 V (90 nA at 3 V) when all DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it an open circuit. This has the advantage that the output is threestate while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 11. The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. In fact, it is possible to load new data to the input registers and DAC registers during power-down. The DAC outputs will update as soon as PD goes high. The time to exit power-down is typically 2.5 ms for VDD = 5 V and 5 ms when VDD = 3 V. This is the time from the rising edge of PD to when the output voltage deviates from its power-down voltage. See TPC 18 for a plot.
AMPLIFIER RESISTOR STRING DAC VOUT
The AD5307/AD5317/AD5327 DACs have double-buffered interfaces consisting of two banks of registers: input registers and DAC registers. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings. Access to the DAC registers is controlled by the LDAC pin. When the LDAC pin is high, the DAC registers are latched and the input registers may change state without affecting the contents of the DAC registers. When LDAC is brought low, however, the DAC registers become transparent and the contents of the input registers are transferred to them. The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user may write to three of the input registers individually and then, by bringing LDAC low when writing to the remaining DAC input register, all outputs will update simultaneously.
POWER-DOWN CIRCUITRY
Figure 11. Output Stage during Power-Down
REV. A
-15-
AD5307/AD5317/AD5327
MICROPROCESSOR INTERFACING ADSP-2101/ADSP-2103 to AD5307/AD5317/AD5327 Interface 80C51/80L51 to AD5307/AD5317/AD5327 Interface
Figure 12 shows a serial interface between the AD5307/AD5317/ AD5327 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 sport is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP's serial clock and clocked into the AD5307/AD5317/AD5327 on the falling edge of the DAC's SCLK.
ADSP-2101/ ADSP-2103*
TFS DT SCLK
AD5307/ AD5317/ AD5327*
SYNC DIN SCLK
Figure 14 shows a serial interface between the AD5307/AD5317/ AD5327 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5307/AD5317/AD5327, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit programmable pin on the port. In this case, port line P3.3 is used. When data is to be transmitted to the AD5307/ AD5317/AD5327, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/ 80L51 outputs the serial data in a format that has the LSB first. The AD5307/AD5317/AD5327 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.
80C51/80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5307/ AD5317/ AD5327*
SYNC SCLK DIN
Figure 12. ADSP-2101/ADSP-2103 to AD5307/ AD5317/AD5327 Interface
68HC11/68L11 to AD5307/AD5317/AD5327 Interface
P3.3 TxD RxD
Figure 13 shows a serial interface between the AD5307/AD5317/ AD5327 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5307/AD5317/ AD5327, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is configured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5307/AD5317/AD5327, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC; PC7 is taken high at the end of this procedure.
68HC11/68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 14. 80C51/80L51 to AD5307/AD5317/AD5327 Interface
MICROWIRE to AD5307/AD5317/AD5327 Interface
Figure 15 shows an interface between the AD5307/AD5317/ AD5327 and any MICROWIRE compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the AD5307/AD5317/AD5327 on the rising edge of SK, which corresponds to the falling edge of the DAC's SCLK.
MICROWIRE*
AD5307/ AD5317/ AD5327*
SYNC SCLK DIN
CS SK SO
AD5307/ AD5317/ AD5327*
SYNC SCLK DIN
*ADDITIONAL PINS OMITTED FOR CLARITY
PC7 SCK MOSI
Figure 15. MICROWIRE to AD5307/AD5317/AD5327 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. 68HC11/68L11 to AD5307/AD5317/ AD5327 Interface
-16-
REV. A
AD5307/AD5317/AD5327
APPLICATIONS Typical Application Circuit Bipolar Operation Using the AD5307/AD5317/AD5327
The AD5307/AD5317/AD5327 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V band gap reference. Figure 16 shows a typical setup for the AD5307/ AD5317/AD5327 when using an external reference.
VDD = 2.5V TO 5.5V
The AD5307/AD5317/AD5327 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 17. This circuit will give an output voltage range of 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. The output voltage for any input code can be calculated as follows:
E REFIN D 2N ( R1 + R2) VOUT = I I R1 - REFIN ( R2 / R1) I
where: D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. with REFIN = 5 V, R1 = R2 = 10 kW:
VOUT = 10 D / 2N - 5V
R2 10k +5V 6V TO 16V 10 F 0.1 F VDD VIN REF195 VOUT GND 1F VOUTA AD820/ OP295 -5V R1 10k 5V
(
)
VIN VOUT EXT REF AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V
0.1 F
10 F VREFAB VOUTA VOUTB
1F
VREFCD
AD5307/AD5317/ AD5327
SCLK DIN SYNC GND SERIAL INTERFACE VOUTC VOUTD
(
)
Figure 16. AD5307/AD5317/AD5327 Using a 2.5 V External Reference
Driving VDD from the Reference Voltage
5V
If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to VDD. As this supply may be noisy and not very accurate, the AD5307/AD5317/AD5327 may be powered from the reference voltage, for example, using a 5 V reference such as the REF195. The REF195 will output a steady supply voltage for the AD5307/AD5317/AD5327. The typical current required from the REF195 is 500 mA supply current and 112 mA into the reference inputs (if unbuffered). This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kW load on each output) is 612 mA + 4(5V / 10 kW) = 2.6 mA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 5.2 ppm (26 mV) for the 2.6 mA current drawn from it. This corresponds to a 0.0013 LSB error at eight bits and 0.021 LSB error at 12 bits.
AD5307/AD5317/ AD5327
VREFAB VREFCD VOUTB VOUTC VOUTD GND DIN SCLK SYNC SERIAL INTERFACE
Figure 17. Bipolar Operation with the AD5307/ AD5317/AD5327
REV. A
-17-
AD5307/AD5317/AD5327
Opto-Isolated Interface for Process Control Applications
The AD5307/AD5317/AD5327 have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. Due to noise, safety requirements, or distance, it may be necessary to isolate the AD5307/AD5317/AD5327 from the controller. This can easily be achieved by using opto-isolators that will provide isolation in excess of 3 kV. The actual data rate achieved may be limited by the type of optocouplers chosen. The serial loading structure of the AD5307/AD5317/AD5327 makes them ideally suited for use in opto-isolated applications. Figure 18 shows an opto-isolated interface to the AD5307/AD5317/AD5327 where DIN, SCLK, and SYNC are driven from optocouplers. The power supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5307/AD5317/AD5327.
AD5307
SCLK DIN VDD VCC ENABLE CODED ADDRESS 1G 1A 1B DGND 74HC139 1Y0 1Y1 1Y2 1Y3 SYNC DIN SCLK VOUTA VOUTB VOUTC VOUTD
AD5307
SYNC DIN SCLK VOUTA VOUTB VOUTC VOUTD
AD5307
SYNC DIN SCLK VOUTA VOUTB VOUTC VOUTD
AD5307
SYNC DIN SCLK VOUTA VOUTB VOUTC VOUTD
POWER
5V REGULATOR
10 F
0.1 F
Figure 19. Decoding Multiple AD5307 Devices in a System
AD5307/AD5317/AD5327 as a Digitally Programmable Window Detector
VDD 10k SCLK SCLK VDD VREFAB VREFCD VDD 10k SYNC SYNC
AD5307
VOUTA VOUTB VOUTC
A digitally programmable upper/lower limit detector using two of the DACs in the AD5307/AD5317/AD5327 is shown in Figure 20. The upper and lower limits for the test are loaded to DACs A and B, which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, an LED will indicate the fail condition. Similarly, DACs C and D can be used for window detection on a second VIN signal.
5V 0.1 F 10 F VIN VDD VOUTA 1/2 CMP04 PASS/FAIL 1k FAIL 1k PASS
VDD 10k DIN DIN DCEN GND
VOUTD
VREF
VREFAB VREFCD
AD5307/AD5317/ AD5327
SYNC SYNC DIN SCLK GND VOUTB DIN SCLK
Figure 18. AD5307 in an Opto-Isolated Interface
Decoding Multiple AD5307/AD5317/AD5327s
1/6 74HC05
The SYNC pin on the AD5307/AD5317/AD5327 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but only the SYNC to one of the devices will be active at any one time, allowing access to four channels in this 16-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 19 shows a diagram of a typical setup for decoding multiple AD5307 devices in a system.
Figure 20. Window Detection
-18-
REV. A
AD5307/AD5317/AD5327
Daisy-Chaining Power Supply Bypassing and Grounding
For systems that contain several DACs, or where the user wishes to read back the DAC contents for diagnostic purposes, the SDO pin may be used to daisy-chain several devices together and provide serial readback. Figure 3 shows the timing diagram for daisy-chain applications. The daisy-chain mode is enabled by connecting DCEN high. See Figure 21.
68HC11* MOSI SCK PC7 PC6 MISO DIN SCLK SYNC LDAC SDO DCEN
AD5307*
DIN
AD5307*
SCLK SYNC LDAC SDO DCEN
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5307/AD5317/AD5327 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5307/AD5317/AD5327 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. The AD5307/AD5317/AD5327 should have ample supply bypassing of 10 mF in parallel with 0.1 mF on the supply located as close to the package as possible, ideally right up against the device. The 10 mF capacitors are the tantalum bead type. The 0.1 mF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. The power supply lines of the AD5307/AD5317/AD5327 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
DIN
AD5307*
SCLK SYNC LDAC SDO DCEN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD5307 in Daisy-Chain Mode
REV. A
-19-
AD5307/AD5317/AD5327
Table II. Overview of AD53xx Serial Devices
Part No. SINGLES AD5300 AD5310 AD5320 AD5301 AD5311 AD5321 DUALS AD5302 AD5312 AD5322 AD5303 AD5313 AD5323 QUADS AD5304 AD5314 AD5324 AD5305 AD5315 AD5325 AD5306 AD5316 AD5326 AD5307 AD5317 AD5327 OCTALS AD5308 AD5318 AD5328
Resolution
No. of DACs
DNL 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0 0.25 0.5 1.0
Interface
Settling Time ( s)
Package
Pins
8 10 12 8 10 12
1 1 1 1 1 1
SPI SPI SPI 2-Wire 2-Wire 2-Wire
4 6 8 6 7 8
SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP
6, 8 6, 8 6, 8 6, 8 6, 8 6, 8
8 10 12 8 10 12
2 2 2 2 2 2
SPI SPI SPI SPI SPI SPI
6 7 8 6 7 8
MSOP MSOP MSOP TSSOP TSSOP TSSOP
8 8 8 16 16 16
8 10 12 8 10 12 8 10 12 8 10 12
4 4 4 4 4 4 4 4 4 4 4 4
SPI SPI SPI 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire 2-Wire SPI SPI SPI
6 7 8 6 7 8 6 7 8 6 7 8
MSOP MSOP MSOP MSOP MSOP MSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
10 10 10 10 10 10 16 16 16 16 16 16
8 10 12
8 8 8
SPI SPI SPI
6 7 8
TSSOP TSSOP TSSOP
16 16 16
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Table III. Overview of AD53xx Parallel Devices
Part No. SINGLES AD5330 AD5331 AD5340 AD5341 DUALS AD5332 AD5333 AD5342 AD5343 QUADS AD5334 AD5335 AD5336 AD5344
Resolution 8 10 12 12 8 10 12 12 8 10 10 12
DNL 0.25 0.5 1.0 1.0 0.25 0.5 1.0 1.0 0.25 0.5 0.5 1.0
VREF Pins 1 1 1 1 2 2 2 1 2 2 4 4
Settling Time ( s) 6 7 8 8 6 7 8 8 6 7 7 8 -20-
Additional Pin Functions BUF GAIN HBEN CLR
Package TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Pins 20 20 24 20 20 24 28 20 24 24 28 28 REV. A

AD5307/AD5317/AD5327
OUTLINE DIMENSIONS 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)
Dimensions shown in millimeters
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 1.20 MAX 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45
0.15 0.05
COMPLIANT TO JEDEC STANDARDS MO-153AB
Revision History
Location 8/03--Data Sheet changed from REV. 0 to REV. A. Page
Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Changes to TPC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Added OCTALS section to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REV. A
-21-
-22-
-23-
-24-
C02067-0-8/03(A)
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